 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Product Preview GS815018/36AB-357/333/300/250 119-Bump BGA Commercial Temp Industrial Temp Features * Register-Register Late Write mode, Pipelined Read mode * 2.5 V +200/-200 mV core power supply * 1.5 V or 1.8 V HSTL Interface * ZQ controlled programmable output drivers * Dual Cycle Deselect * Fully coherent read and write pipelines * Byte write operation (9-bit bytes) * Differential HSTL clock inputs, K and K * Asynchronous output enable * Sleep mode via ZZ * IEEE 1149.1 JTAG-compliant Serial Boundary Scan * JEDEC-standard 119-bump BGA package * Pb-Free 119-bump BGA package available 1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM Functional Description 250 MHz-357 MHz 2.5 V VDD HSTL I/O Because GS815018/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing. GS815018/36A support pipelined reads utilizing a rising-edgetriggered output register. They also utilize a Dual Cycle Deselect (DCD) output deselect protocol. GS815018/36A are implemented with high performance technology and are packaged in a 119-bump BGA. Family Overview GS815018/36A are 18,874,368-bit (18Mb) high performance SRAMs. This family of wide, low voltage HSTL I/O SRAMs is designed to operate at the speeds needed to implement economical high performance cache systems. Mode Control There are two mode control select pins (M1 and M2), which allow the user to set the correct read protocol for the design. The GS815018/36A support single clock Pipeline mode, which directly affects the two mode control select pins. In order for the part to fuction correctly, and as specified, M1 must be tied to VSS and M2 must be tied to VDD or VDDQ. This must be set at power-up and should not be changed during operation. Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Parameter Synopsis -357 Pipeline Cycle tKHQV Curr (x18) Curr (x36) 2.8 1.4 600 650 -333 3.0 1.5 550 600 -300 3.3 1.6 500 550 -250 4.0 2.0 450 500 Unit ns ns mA mA Rev: 1.05 10/2005 1/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 GS815036 Pinout--119-Bump BGA--Top View (Package B) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A A A DQC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQD A NC TMS 3 A A A VSS VSS VSS BC VSS VREF VSS BD VSS VSS VSS M1 A TDI 4 NC NC VDD ZQ SS G NC NC VDD CK CK SW A A VDD A TCK 5 A A A VSS VSS VSS BB VSS VREF VSS BA VSS VSS VSS M2 A TDO 6 A A A DQB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQA A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ Rev: 1.05 10/2005 2/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 GS815018 Pinout--119-Bump BGA--Top View (Package B) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC VDDQ 2 A A A NC DQB NC DQB NC VDD DQB NC DQB NC DQB A A TMS 3 A A A VSS VSS VSS BB VSS VREF VSS NC VSS VSS VSS M1 A TDI 4 NC NC VDD ZQ SS G NC NC VDD CK CK SW A A VDD NC TCK 5 A A A VSS VSS VSS NC VSS VREF VSS BA VSS VSS VSS M2 A TDO 6 A A A DQA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ Rev: 1.05 10/2005 3/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 GS815018/36 BGA Pin Description Symbol A DQA DQB DQC DQD BA, BB, BC, BD NC CK CK SW G ZZ M1 M2 ZQ SS TMS TDI TDO TCK VREF VDD VSS VDDQ Type I I/O I -- I I I I I I I I I I I O I I I I I Description Address Inputs Data Input and Output pins Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low No Connect Clock Input Signal; active high Clock Input Signal; active low Write Enable; active low Output Enable; active low Sleep mode control; active high Read Operation Protocol Select--Selects Register-Register read operations; must be tied low in this device Read Operation Protocol Select--Selects Register-Register read operations; must be tied high in this device FLXDrive-IITM Output Impedance Control Synchronous Select Input Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Input Reference Voltage Core power supply I/O and Core Ground Output driver power supply Read Operations Pipelined Read A read cycle begins when the RAM captures logic 0 on SS and logic 1 on SW at the rising edge of K (and the falling edge of K). Address inputs captured on that clock edge are propigated into the RAM, which delivers data to the input of the output registers. The second rising edge of K fires the output registers and releases read data to the output drivers. If G is held active low, the drivers drive the data onto the output pins. Read data is sustained on the output pins as long as G is held low or until the next rising edge of K, at which point the outputs may update to new data or deselect, depending on what control command was registered at the second rising edge of K. Dual Cycle Deselect Chip deselect (SS = logic 1) is pipelined to the same degree as read data. Therefore, a deselect command entered on the rising edge of K is acted upon in response to the next rising edge of K. Rev: 1.05 10/2005 4/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Write Operations Write operations are initiated when the write enable input signal (SW) and chip select (SS) are captured at logic 0 on a rising edge of the K clock (and falling edge of the K clock). Late Write In Late Write mode the RAM requires Data In one rising clock edge later than the edge used to load Address and Control. Late Write protocol has been employed on SRAMs designed for RISC processor L2 cache applications and in Flow Through mode NBT SRAMs. Byte Write Control The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins, including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle. Byte write control inputs are captured by the same clock edge used to capture SW. Example of x36 Byte Write Truth Table Function Read Write Byte A Write Byte B Write Byte C Write Byte D Write all Bytes Write Abort SW H L L L L L L Ba X L H H H L H Bb X H L H H L H Bc X H H L H L H Bd X H H H L L H Rev: 1.05 10/2005 5/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Register-Register Late Write, Pipelined Read Truth Table CK X ZZ 1 0 0 0 0 0 0 SS X 1 0 0 0 0 0 SW X X 1 1 0 0 0 Bx X X X X 0 X 1 G X X 1 0 X X X Current Operation Sleep (Power Down) mode Deselect Read Read Write All Bytes Write Bytes with Bx = 0 Write (Abort) DQ (tn) Hi-Z *** Hi-Z/ *** *** *** *** DQ (tn+1) Hi-Z Hi-Z Hi-Z Q(tn) D(tn) D(tn) Hi-Z Notes: 1. If one or more Bx = 0, then B = "T" else B = "F". 2. "1" = input "high"; "0" = input "low"; "X" = input "don't care". 3. "***" indicates that the DQ input requirement/output state and CQ output state are determined by the previous operation. 4. DQs are tristated in response to Bank Deselect, Deselect, and Write commands, one full cycle after the command is sampled. 5. CQs are tristated in response to Bank Deselect commands only, one full cycle after the command is sampled. 6. Up to three (3) Continue operations may be initiated after a Read or Write operation is initiated to burst transfer up to four (4) distinct pieces of data per single external address input. If a fourth (4th) Continue operation is initiated, the internal address wraps back to the initial external (base) address. Rev: 1.05 10/2005 6/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Absolute Maximum Ratings (All voltages reference to VSS) Symbol VDD VDDQ VI/O VIN IIN IOUT TJ TSTG Description Voltage on VDD Pins Voltage in VDDQ Pins Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Maximum Junction Temperature Storage Temperature Value -0.5 to 3.6 -0.5 to VDD -0.5 to VDDQ + 0.5 ( 3.6 V max.) -0.5 to VDDQ + 0.5 ( 3.6 V max.) +/-20 +/-20 125 -55 to 125 Unit V V V V mA dc mA dc oC C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component. Recommended Operating Conditions Power Supplies Parameter Supply Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions) Symbol VDD TA TA Min. 2.3 0 -40 Typ. 2.5 25 25 Max. 2.7 70 85 Unit V C C Notes 1 Note: The part number of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. Rev: 1.05 10/2005 7/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Common Mode and Differential Voltage 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 Volts 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8 0 20 40 60 Time 80 100 120 VCM K K# VCM VDIF Undershoot Measurement and Timing VIH Overshoot Measurement and Timing 20% tKC VDD + 1.0 V VSS 50% VSS - 1.0 V 20% tKC 50% VDD VIL Rev: 1.05 10/2005 8/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Capacitance (TA = 25oC, f = 1 MHZ, VDD = 1.8 V) Parameter Input Capacitance Output Capacitance Output Capacitance (Clock) Note: This parameter is sample tested. Symbol CIN COUT CIN(CK) Test conditions VIN = 0 V VOUT = 0 V VIN = 0 V Max. 4 5 5 Unit pF pF pF AC Test Conditions Parameter Input high level Input low level Input rise/fall time (10% to 90%) Input reference level Clock input reference level Output reference level Clock (VDIF) Clock (VCM) VDDQ RQ Conditions 1.25 V 0.25 V 0.5 ns/0.5 ns VDDQ/2 Differential cross point VDDQ/2 0.75 V 0.75 V 1.5 V 250 AC Test Load Diagram 50 Device Under Test VDDQ = 1.5 V DQ ZQ 25 50 5pF VDDQ/2 50 50 5pF VDDQ/2 VDDQ/2 RQ = 250 Rev: 1.05 10/2005 9/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Input and Output Leakage Characteristics Parameter Input Leakage Current (except mode pins) ZQ, MCH, MCL, EP2, EP3 Pin Input Current Output Leakage Current Symbol IIL IINM IOL Test Conditions VIN = 0 to VDDQ VIN = 0 to VDDQ Output Disable, VOUT = 0 to VDDQ Min. -1 uA -100 uA -1 uA Max 1 uA 1 uA 1 uA Notes -- -- -- Operating Currents -357 Parameter Symbol IDD IDD -333 0C to 70C 600 mA 550 mA -300 0C to 70C 550 mA 500 mA -250 0C to 70C 500 mA 450 mA 0C to 70C 650 mA 600 mA -40C to +85C 660 mA 610 mA -40C to +85C 610 mA 560 mA -40C to +85C 560 mA 510 mA -40C to +85C 510 mA 460 mA Test Conditions SS VIL Max. tKHKH tKHKH Min. All other inputs VIL VIN VIH Device Deselected All inputs VSS + 0.10 V VIN VDD - 0.10 V x36 Operating Current x18 HSTL Deselect Current IDD3 150 mA 160 mA 150 mA 160 mA 150 mA 160 mA 150 mA 160 mA Rev: 1.05 10/2005 10/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 AC Electrical Characteristics Parameter Clock Cycle Time Clock High Time Clock Low Time Clock High to Output Low-Z Clock High to Output Valid Clock High to Output Invalid Clock High to Output High-Z Address Valid to Clock High Clock High to Address Don't Care Enable Valid to Clock High Clock High to Enable Don't Care Write Valid to Clock High Clock High to Write Don't Care Byte Write Valid to Clock High Clock High to Byte Write Don't Care Data In Valid to Clock High Clock High to Data In Don't Care Output Enable Low to Output Data Valid Output Enable Low to Output Data Low-Z Output Enable High to Output Data High-Z Sleep Mode Enable Time Sleep Mode Recovery Time Symbol tKHKH tKHKL tKLKH tKHQX1 tKHQV tKHQX tKHQZ tAVKH tKHAX tEVKH tKHEX tWVKH tKHWX tBVKH tKHBX tDVKH tKHDX tGLQV tGLQX tGHQZ tZZE tZZR -357 Min 2.8 1.1 1.1 0.5 -- 0.5 -- 0.5 0.4 0.5 0.4 0.5 0.4 0.5 0.4 0.5 0.4 -- 0 -- -- 20 Max -- -- -- -- 1.4 -- 1.4 -- -- -- -- -- -- -- -- -- -- 1.4 -- 1.4 15 -- -333 Min 3.0 1.2 1.2 0.5 -- 0.5 -- 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.5 0.4 -- 0 -- -- 20 Max -- -- -- -- 1.5 -- 1.5 -- -- -- -- -- -- -- -- -- -- 1.5 -- 1.5 15 -- -- 20 0 0.7 0.4 0.7 0.4 0.7 0.4 0.7 0.4 0.5 0.4 0.5 -300 Min 3.3 1.3 1.3 0.5 Max -- -- -- -- 1.6 -- 1.6 -- -- -- -- -- -- -- -- -- -- 1.6 -- 1.6 15 -- -250 Min 4.0 1.5 1.5 0.5 -- 0.5 -- 0.8 0.5 0.8 0.5 0.8 0.5 0.8 0.5 0.5 0.5 -- 0 -- -- 20 Max -- -- -- -- 2.0 -- 2.0 -- -- -- -- -- -- -- -- -- -- 2.0 -- 2.0 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes -- -- -- 1 -- -- 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Notes: 1. Measured at 100 mV from steady state. Not 100% tested. 2. Guaranteed by design. Not 100% tested. Rev: 1.05 10/2005 11/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 G Controlled Read-Write Read A1 KHKL KHKH K tAVKH tKHAX A G tWVKH tKHWX SW tWVKH tKHWX BWx KHQX GLQV GLQX DQn Q1 Q2 A1 A2 A0 A3 A4 A5 A4 A6 A7 Read A2 Read A0 Write A3 Write A4 Read A5 Read A4 Read A6 Read A7 KLKH GHQZ D3 DVKH KHDX D4 KHQV KHQX1 Q5 Q4 Q6 Note: K is not shown; assumes K tied to VREF or out of phase with K SS Controlled Read-Write Read A1 KHKL KHKH K tAVKH tKHAX A A1 A2 A3 A4 A5 A4 A6 A7 Read A2 Deselect Write A3 Write A4 Read A5 Read A4 Read A6 Read A7 KLKH tEVKH tKHEX SS tWVKH tKHWX SW tBVKH tKHBX BWx KHQZ KHQX1 DQn Q1 KHQV Q2 D3 D4 tDVKH tKHDX Q5 KHQX Q4 Note: K is not shown; assumes K tied to VREF or out of phase with K Rev: 1.05 10/2005 12/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 ZZ Timing Read A1 KHKL KHKH K tAVKH tKHAX A A1 A2 A1 A2 A3 Read A2 Deselect Clock is a Don't care during Sleep ModeRead A1 Read A2 Read A3 KLKH tEVKH tKHEX SS tWVKH tKHWX SW SWx Begin ISB ZZR ZZ ZZE KHQX1 DQn Q1 Q2 KHQX KHQV Q1 Note: K is not shown; assumes K tied to VREF or out of phase with K JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. Rev: 1.05 10/2005 13/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 JTAG Port Registers JTAG Pin Descriptions Pin TCK TMS Pin Name Test Clock Test Mode Select I/O In In Description Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.05 10/2005 14/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 JTAG TAP Block Diagram * * * 108 * * * * * * * * 1 Boundary Scan Register 0 Bypass Register 210 0 Instruction Register TDI ID Code Register 31 30 29 TDO * *** 210 Control Signals TMS TCK Test Access Port (TAP) Controller Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Rev: 1.05 10/2005 15/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Tap Controller Instruction Set ID Register Contents Die Revision Code Bit # x36 x18 GSI Technology JEDEC Vendor ID Code Presence Register 0 1 1 Not Used I/O Configuration 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X 0 0 0 0 0 0 X X 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 011011001 0 011011001 Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.05 10/2005 16/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 JTAG Tap Controller State Diagram 1 Test Logic Reset 0 1 1 1 0 Run Test Idle Select DR 0 1 Select IR 0 1 Capture DR 0 Capture IR 0 Shift DR 1 1 0 1 Shift IR 1 0 Exit1 DR 0 Exit1 IR 0 Pause DR 1 0 Pause IR 1 0 Exit2 DR 1 0 Exit2 IR 1 0 Update DR 1 0 Update IR 1 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. Rev: 1.05 10/2005 17/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.05 10/2005 18/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 JTAG Port AC Test Conditions Parameter Input high level Input low level Input slew rate Input reference level Output reference level Conditions VDD - 0.2 V 0.2 V 1 V/ns VDDQ/2 VDDQ/2 DQ JTAG Port AC Test Load 50 VDDQ/2 * Distributed Test Jig Capacitance 30pF* Notes: 1. Include scope and jig capacitance. 2. Test conditions as shown unless otherwise noted. JTAG TAP Instruction Set Summary Instruction EXTEST IDCODE SAMPLE-Z Code 000 001 010 Description Places the Boundary Scan Register between TDI and TDO. Preloads ID Register and places it between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. GSI private instruction. Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. Places Bypass Register between TDI and TDO. Notes 1 1, 2 1 RFU SAMPLE/ PRELOAD GSI RFU BYPASS 011 100 101 110 111 1 1 1 1 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.05 10/2005 19/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 JTAG Port Recommended Operating Conditions and DC Characteristics Parameter 3.3 V Test Port Input High Voltage 3.3 V Test Port Input Low Voltage 2.5 V Test Port Input High Voltage 2.5 V Test Port Input Low Voltage TMS, TCK and TDI Input Leakage Current TMS, TCK and TDI Input Leakage Current TDO Output Leakage Current Test Port Output High Voltage Test Port Output Low Voltage Test Port Output CMOS High Test Port Output CMOS Low Symbol VIHJ3 VILJ3 VIHJ2 VILJ2 IINHJ IINLJ IOLJ VOHJ VOLJ VOHJC VOLJC Min. 2.0 -0.3 0.6 * VDDQ2 -0.3 -300 -1 -1 1.7 -- VDDQ - 100 mV -- Max. VDD3 +0.3 0.8 VDDQ2 +0.3 0.3 * VDDQ2 1 100 1 -- 0.4 -- 100 mV Unit Notes V V V V uA uA uA V V V V 1 1 1 1 2 3 4 5, 6 5, 7 5, 8 5, 9 Notes: 1. Input Under/overshoot voltage must be -1 V > Vi < VDDn +1 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDQ 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDQ 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = -4 mA 7. IOLJ = + 4 mA 8. IOHJC = -100 uA 9. IOLJC = +100 uA Rev: 1.05 10/2005 20/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 JTAG Port Timing Diagram tTKC TCK tTH tTS TDI tTH tTS TMS tTKQ TDO tTH tTS Parallel SRAM input tTKH tTKL JTAG Port AC Electrical Characteristics Parameter TCK Cycle Time TCK Low to TDO Valid TCK High Pulse Width TCK Low Pulse Width TDI & TMS Set Up Time TDI & TMS Hold Time Symbol tTKC tTKQ tTKH tTKL tTS tTH Min 50 -- 20 20 10 10 Max -- 20 -- -- -- -- Unit ns ns ns ns ns ns Rev: 1.05 10/2005 21/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Package Dimensions--119-Bump FPBGA (Package B, Variation 2) A1 1 A B C D E F G H J K L M N P R T U TOP VIEW BOTTOM VIEW A1 O0.10S C O0.30S C AS B S O0.60~0.90 (119x) 2 3 4 5 6 7 7 6 5 43 2 1 A B C D E F G H J K L M N P R T U 220.10 B 1.27 7.62 0.15 C A 0.20(4x) 140.10 Rev: 1.05 10/2005 0.50~0.70 1.86.0.13 C SEATING PLANE 22/25 20.32 1.27 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Ordering Information Org 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 1M x 18 1M x 18 Part Number GS815018AB-357 GS815018AB-333 GS815018AB-300 GS815018AB-250 GS815036AB-357 GS815036AB-333 GS815036AB-300 GS815036AB-250 GS815018AB-357I GS815018AB-333I GS815018AB-300I GS815018AB-250I GS815036AB-357I GS815036AB-333I GS815036AB-300I GS815036AB-250I GS815018AGB-357 GS815018AGB-333 GS815018AGB-300 GS815018AGB-250 GS815036AGB-357 GS815036AGB-333 GS815036AGB-300 GS815036AGB-250 GS815018AGB-357I GS815018AGB-333I Type Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM I/O Speed (MHz) 357 MHz 333 MHz 300 MHz 250 MHz 357MHz 333 MHz 300 MHz 250 MHz 357 MHz 333 MHz 300 MHz 250 MHz 357 MHz 333 MHz 300 MHz 250 MHz 357 MHz 333 MHz 300 MHz 250 MHz 357MHz 333 MHz 300 MHz 250 MHz 357 MHz 333 MHz TA C C C C C C C C I I I I I I I I C C C C C C C C I I Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS815036AB-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.05 10/2005 23/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 Ordering Information Org 1M x 18 1M x 18 512K x 36 512K x 36 512K x 36 512K x 36 Part Number GS815018AGB-300I GS815018AGB-250I GS815036AGB-357I GS815036AGB-333I GS815036AGB-300I GS815036AGB-250I Type Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM Pb-Free Register-Register Late Write SRAM I/O Speed (MHz) 300 MHz 250 MHz 357 MHz 333 MHz 300 MHz 250 MHz TA I I I I I I Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS815036AB-300T. 2. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. Rev: 1.05 10/2005 24/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Product Preview GS815018/36AB-357/333/300/250 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New 8150xxA_r1 8150xxA_r1; 8150xxA_r1_01 8150xxA_r1_01; 8150xxA_r1_02 8150xxA_r1_02; 8150xxA_r1_03 8150xxA_r1_03; 8150xxA_r1_04 8150xxA_r1_04; 8150xxA_r1_05 Content/Format Types of Changes Format or Content Page;Revisions;Reason * Creation of new datasheet * Corrected L3 from VSS to NC * Updated entire format * Placed corrected BGA diagram in document * Updated format * Added variation information to 119 BGA mechanical drawing * Updated AC Characteristics table * Updated /G Controlled Read-Write timing diagram * Updated JTAG Port Rec. Op Con & DC Char table * Pb-Free information added * Changed VDD to max 3.6 V for 8150xxA Content/Format Content Content Content Rev: 1.05 10/2005 25/25 (c) 2003, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. |
Price & Availability of GS815018AGB-357
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |